1. Field of the Invention
The present invention relates generally to a method and an apparatus for etching copper (Cu), and more particularly to anisotropic etching of copper using passivation.
2. Description of Background Art
Copper (Cu) is emerging as the metal of choice in a wide variety of semiconductor applications. Lower electrical resistivity, coupled with improved electromigration performance and increased stress migration resistance are important material properties that favor the use of Cu over aluminum (Al) in interconnect lines and contacts. The lower electrical resistance allows signals to move faster by reducing the RC time delay. The superior resistance to electromigration, a common reliability problem in Al lines, means that Cu can handle higher power densities.
The capability to process substrates anisotropically permits the production of integrated circuit features at precisely defined locations with sidewalls that are essentially perpendicular to the surface of a masked overlayer. Anisotropic etch of Al by reactive ion etching (RIE) is well developed. For example, use of a chloride to form aluminum chloride as a by-product of the etch reaction provides good results at low temperatures. However, Cu is more difficult to etch because copper chloride forms at much higher temperatures than aluminum chloride. Thus, the introduction of Cu into multilevel metallization architecture has led to new processing methods for Cu patterning, such as the damascene approach.
The damascene approach is based on etching features in a dielectric material, filling such features with Cu metal, and chemically and physically polishing the Cu thin film by using a CMP method while leaving Cu only in the grooves. Dual damascene schemes integrate both the contacts and the interconnect lines into a single processing scheme. However, the damascene method includes complicated processes which make it difficult to define extremely fine features, and CMP suffers from yield-detracting problems of scratching, peeling, dishing and erosion. Further, overwhelming electron scattering at copper grain boundaries from the standard plating-CMP steps will likely have an adverse effect on transistor speed due to its resultant RC delay in the post ˜14 nm generation technology (i.e., line width regime less than 30 nm). Thus, continued use of the damascene process for Cu patterning is unlikely and there is a need to develop improved reliable Cu etch techniques (as in the case of Al) for next generation device fabrication.
It is also expected that after dry etching copper of a large number of wafers, the chamber condition may become severely altered. As such, chamber stability is expected to suffer and the etching results are expected to drift. Thus, there is also a need to clean off the Cu deposits on the surfaces of the chamber parts, restoring the proper seasoning condition of the chamber.